Compiled Code Acceleration on Fpgas
نویسندگان
چکیده
The ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C-to-VHDL compiler used to compile routines written in a subset of C to an application-specific circuit on an FPGA. ROCCC incorporates several powerful parallelizing transformations targeted towards code generation for FPGAs and can achieve performance comparable to hand-coded VHDL. We have demonstrated speedups ranging from 800x to several 1,000x over the Itanium 2 1.6 GHz on an SGI Altix 4700 with one RASC RC 100 blade.
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تاریخ انتشار 2007